FIG. 13 is a diagram showing a configuration of a conventional sense amplifier circuit constituted from a flip-flop type voltage comparator circuit. This sense amplifier circuit (flip-flop type voltage comparator circuit) cancels an offset resulting from manufacturing variations in transistors. More specifically, referring to FIG. 13, this sense amplifier circuit includes PMOS transistors MP91 and MP92 with sources thereof connected in common to a power supply Ssp, drains thereof connected to bit lines (a bit line pair of) BL1 and BL2, respectively, and gates thereof connected to the bit lines BL2 and BL1, respectively, and NMOS transistors MN91 and MN92 with sources thereof connected in common to a power supply Ssn, drains thereof connected to the bit line BL1 through a switch SW92 and to the bit line BL2 through a switch SW94, respectively, and gates thereof connected to the bit line BL2 through a capacitance C91 and to the bit line BL1 through a capacitance C92, respectively. A switch SW91 is disposed between a gate of the NMOS transistor MN91 and a drain of the NMOS transistor MN91, while a switch SW93 is disposed between a gate of the NMOS transistor MN92 and a drain of the NMOS transistor MN92.
FIG. 14 is a timing waveform diagram for explaining an operation of the circuit in FIG. 13. FIGS. 15, 16, and 17 are diagrams showing connections of the circuit in FIG. 13 at respective timings shown in FIG. 14. Incidentally, the switches that are in an off state in FIG. 13 are not illustrated in FIGS. 15, 16, and 17.
In the following an analysis is given according to the present invention.
When the power supplies Ssn and Ssp and the bit lines BL1 and BL2 are set to a potential VCC/2, and when the switches SW91, SW92, SW93, and SW94 are turned on, as shown in FIG. 15, potentials at both ends of the capacitances C91 and C92 become the same potential of VCC/2, respectively. An electric charge in each of the capacitances C91 and C92 is reset to nil.
When the switches SW92 and SW94 that were in the on state in FIG. 15 are turned off (refer to a timing (b) in FIG. 14) and when the power supply Ssn is reduced from the potential VCC/2 to a potential Vdc (refer to a period Ta in FIG. 14), as shown in FIG. 16, the NMOS transistors MN91 and MN92 are turned on. Thus, a source follower operation of a diode connection occurs at each of the transistors. This causes a gate voltage of the NMOS transistor MN91 to become (Vdc+Vtn91) and a gate voltage of the NMOS transistor MN92 to become (Vdc+Vtn92), in which Vtn91 and Vtn92 are threshold voltages of the NMOS transistors MN91 and MN92, respectively. A potential difference between the gate voltage of the MOS transistor MN91 and the potential VCC/2 and a potential difference between the gate voltage of the MOS transistor MN92 and the potential VCC/2 are held in the capacitances 91 and 92, respectively.
As shown in FIG. 17, the switches SW91 and SW93 which were in the on state in FIG. 16 are turned off, the switches SW92 and SW94 that were in the off state in FIG. 16 are turned on, the power supply Ssn becomes a GND potential, and the power supply Ssp becomes a power supply voltage VCC (refer to a timing (c) in FIG. 14). Since source potentials Ssn of the NMOS transistors MN91 and MN92 are reduced, gate-to-source voltages of the NMOS transistors MN91 and MN92 increase, and the same current flows through each of the transistors.
When a voltage (VCC/2+Δ) is applied to the bit line BL1 as data, the gate voltages of the transistors MP92 and MN92 increase just by the voltage Δ, respectively. For this reason, a potential at the bit line BL2 is reduced because a drain current (source-to-drain current) of the PMOS transistor MP92 is reduced and a drain current (drain-to-source current) of the NMOS transistor MN92 is increased. A potential at the bit line BL1 is increased because a drain current (source-to-drain current) of the PMOS transistor MP91 is increased and a drain current (drain-to-source current) of the NMOS transistor MN91 is reduced due to reduction of a potential at the bit line BL2.
As a result, it becomes that BL1=VCC, and BL2=GND, and the bit lines become stabilized.
In the flip-flop type voltage comparator circuit in FIG. 13, the potential difference (Vt+Vdc) is stored in each of the capacitances due to the source follower operations of the transistors MN91 and MN92 which are diode-connected in the period Ta (refer to FIG. 14). An operation on data, which does not depend on the threshold voltage Vt can be thereby performed.
As a configuration for canceling the offset caused by the manufacturing variations in transistors in the flip-flop type voltage comparator circuit, a configuration as shown in FIG. 18, for example, is known (refer to Patent Document 2). FIG. 19 is a timing diagram showing on and off control over switches in FIG. 18, and FIGS. 20 through 22 are diagrams showing connecting configurations of a circuit in FIG. 18 in respective steps in FIG. 19, respectively.
In the following an analysis is given according to the present invention.
Referring to FIG. 18, this flip-flop type voltage comparator circuit includes a PMOS transistor MP83 with a source thereof connected to a power supply VDD and a gate thereof connected to a signal STBB (which is a complementary signal of a signal STB), PMOS transistors MP81 and MP82 with sources thereof connected to a drain of the PMOS transistor MP83, an NMOS transistor MN83 with a source thereof connected to a power supply VSS and a gate thereof connected to the signal STB, and NMOS transistors MN81 and MN82 with sources thereof connected in common to a drain of the NMOS transistor MN83 and drains thereof connected to drains of the PMOS transistors MP81 and MP82, respectively.
Gates of the PMOS transistor MP81 and the NMOS transistor MN81 are connected in common to an input signal VI through a capacitance C81 and a switch SW85. Gates of the PMOS transistor MP82 and the NMOS transistor MN82 are connected in common to a reference signal VR through a capacitance C82 and a switch SW87. Between the gates of the PMOS transistor MP81 and the NMOS transistor MN81 connected in common and the drains of the PMOS transistor MP81 and the NMOS transistor MN81 connected in common, a switch SW83 is provided. Between the gates of the PMOS transistor MP82 and the NMOS transistor MN82 connected in common and the drains of the PMOS transistor MP82 and the NMOS transistor MN82 connected in common, a switch SW84 is provided. Between the drains of the PMOS transistor MP81 and the NMOS transistor MN81 connected in common and the gates of the PMOS transistor MP82 and the NMOS transistor MN82 connected in common, a switch SW81 is provided. Between the drains of the PMOS transistor MP82 and the NMOS transistor MN82 connected in common and the gates of the PMOS transistor MP81 and the NMOS transistor MN81 connected in common, a switch SW82 is provided. A switch SW86 is provided between a connecting point between the capacitance C81 and the switch SW85 and a connecting point between the capacitance C82 and the switch SW87. On and off control over the switches SW81 to SW87 is performed by a control signal (not shown).
In this flip-flop type voltage comparator circuit, the common gate of the MOS transistors MN81 and MP81 that constitute an inverter and the common gate of the MOS transistors MN82 and MP82 that constitute an inverter are each reset to a logic inversion voltage (voltage at which an input of the inverter coincides with an output of the inverter) in advance, and to one of the common gates, a potential difference between the reference signal and an input data signal, that becomes positive or negative with respect to the reference signal is given. Then, the strobe signal STB and the inverted signal STBB of the strobe signal STB are given to the gates of the MOS transistors MN83 and MP83, respectively. When the flip-flop circuit is activated, a positive feedback is applied, and the potential difference between the common gates is amplified. With this arrangement, even if the potential difference between the reference signal and the data signal is small, voltage comparison between these signals can be performed at high speed. An operation of the voltage comparison will be described below.
Referring to FIGS. 19 and 20, in step 1, the strobe signal STB is driven HIGH, the switches SW81 and SW82 are turned off, the switches SW83, SW84, and SW86 are turned on, the switch SW85 is turned off, and the switch SW87 is turned on. A drain and the gate of each of the PMOS transistor MP81 and the NMOS transistor MN81 that constitute the inverter are connected (diode-connected), and a drain and the gate of each of the PMOS transistor MP82 and the NMOS transistor MN82 that constitutes the inverter are connected (diode-connected). In this case, the input of each of the inverters coincides with the output of each of the inverters, and respective voltages VA and VB of the inverters become logic inversion voltages. Then, potential differences between the reference signal VR and the respective logic inversion voltages VA and VB of the inverters are stored in the capacitances C81 and C82, respectively.
The logic inversion voltages VA and VB become different voltages when variations in elements are present. However, by holding a potential difference between each logic inversion voltage and the reference signal VR in the corresponding capacitance, an operation that does not depend on the variations in elements becomes possible.
Next, referring to FIGS. 19 and 21, in step 2, the strobe signal STB is driven LOW, the signal STBB is driven HIGH, and the MOS transistors MP83 and MN83 are turned off. The switches SW81 and SW82 are kept off, the switches SW83, SW84, and SW86 are turned off, and the switch SW85 is turned on. The switch SW87 is kept on. The common source of the NMOS transistors MN81 and MN82 and the common source of the PMOS transistors MP81 and MP82 are brought to a floating state. The reference signal VR is consecutively applied to one end of the capacitance C82, while the input signal VI is consecutively applied to one end of the capacitance C81. With this arrangement, a voltage VI is added to a voltage (VA−VR) stored in the capacitance C81 in step 1, and gate voltages of the MOS transistors MN81 and MP81 thereby become VI+(VA−VR)=(VI−VR)+VA. That is, the gate voltages of the MOS transistors MN81 and M81 become a voltage shifted from a logic inversion voltage VA just by a voltage difference (VI−VR) between the input signal VI and the reference signal VR.
Referring to FIGS. 19 and 22, in step 3, the strobe signal STB is driven HIGH, the switches SW81 and SW82 are turned on, the switches SW83, SW84, and SW86 are kept off, and the switches SW85 and SW87 are turned off. When the MOS transistors MP83 and MN83 are turned on and when the flip-flop circuit is activated, a voltage VO at the common drain of the MOS transistors MP81 and MN81 (an output voltage of the flip-flop circuit) changes according to the common gate voltage {(VI−VR)+VA}.
When VI>VR, the common gate of the MOS transistors MN81 and MP81 that constitute the inverter has a higher potential than the voltage VA. Thus, the output voltage VO is lowered when the flip-flop circuit (constituted from the MOS transistors MN81, MN82, MP81, and MP82) is activated, resulting in VO=VSS, where the output voltage VO is stabilized.
On the other hand, when VI<VR, the common gate of the MOS transistors MN81 and MP81 has a lower potential than the voltage VA. Thus, the output voltage VO is elevated when the flip-flop circuit is activated, resulting in VO=VDD.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-62-273694
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-5-218825